`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/05/28 09:19:10
// Design Name: 
// Module Name: Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Top
(
  //ddr4-物理接口
  input             sys_rstn        ,//复位按键
  input             c0_sys_clk_n    ,
  input             c0_sys_clk_p    ,
  output            c0_ddr4_act_n   ,
  output    [16:0]  c0_ddr4_adr     ,
  output    [1:0]   c0_ddr4_ba      ,
  output    [0:0]   c0_ddr4_bg      ,
  output    [0:0]   c0_ddr4_ck_c    ,
  output    [0:0]   c0_ddr4_ck_t    ,
  output    [0:0]   c0_ddr4_cke     ,
  output    [0:0]   c0_ddr4_cs_n    ,
  inout     [7:0]   c0_ddr4_dm_n    ,
  inout     [63:0]  c0_ddr4_dq      ,
  inout     [7:0]   c0_ddr4_dqs_c   ,
  inout     [7:0]   c0_ddr4_dqs_t   ,
  output    [0:0]   c0_ddr4_odt     ,
  output            c0_ddr4_reset_n 
);


wire init_calib_complete            ;
wire [15:0]     data_out            ;
wire [255:0]    ud_wdata            ;

assign ud_wdata = { data_out,data_out,      //ch1
                    data_out,data_out,      //ch2
                    data_out,data_out,      //ch3
                    data_out,data_out,      //ch4
                    data_out,data_out,      //ch5
                    data_out,data_out,      //ch6
                    data_out,data_out,      //ch7
                    data_out,data_out };    //ch8

system_wrapper system_wrapper
(
.c0_ddr4_act_n  (c0_ddr4_act_n  ),
.c0_ddr4_adr    (c0_ddr4_adr    ),
.c0_ddr4_ba     (c0_ddr4_ba     ),
.c0_ddr4_bg     (c0_ddr4_bg     ),
.c0_ddr4_ck_c   (c0_ddr4_ck_c   ),
.c0_ddr4_ck_t   (c0_ddr4_ck_t   ),
.c0_ddr4_cke    (c0_ddr4_cke    ),
.c0_ddr4_cs_n   (c0_ddr4_cs_n   ),
.c0_ddr4_dm_n   (c0_ddr4_dm_n   ),
.c0_ddr4_dq     (c0_ddr4_dq     ),
.c0_ddr4_dqs_c  (c0_ddr4_dqs_c  ),
.c0_ddr4_dqs_t  (c0_ddr4_dqs_t  ),
.c0_ddr4_odt    (c0_ddr4_odt    ),
.c0_ddr4_reset_n(c0_ddr4_reset_n),
.c0_sys_clk_n   (c0_sys_clk_n   ),
.c0_sys_clk_p   (c0_sys_clk_p   ),
.sys_rst        (sys_rst        ),

.init_calib_complete    (init_calib_complete),
.data_out       (data_out       ),
.ud_wdata       (ud_wdata       )
);
endmodule
